Without limiting the scope of the invention, its background is described in connection with an electrically-programmable read-only-memory (EPROM), as an example.
There is a continuing demand for increased bit density in integrated circuit memory devices, such as EPROMs. One technique for increasing bit density in EPROMs is the use of a virtual ground configuration. A virtual ground configuration provides an increase in bit density over dedicated ground configurations by eliminating the need for a separate ground line for each column.
Virtual ground arrays are constructed from rows of memory cells with common gates called wordlines. Common drain diffusions form drain column lines or bitlines. Common source diffusions form source column lines or array source lines. In EPROM arrays bits are programmed by placing a high voltage on a selected bitline and word line and connecting a selected array source line to ground or by placing a high voltage on a selected array source line and wordline and connecting a selected bitline to ground. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen wordline select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage is applied to the control gate. The conductive state is read as a "one" bit. For an EPROM virtual ground array it is important that one array section, bounded by outermost columns have only one ground path between the high voltage bitline and the grounded array source line to avoid inadvertent programming. Since EPROMs usually program data in bytes, previous virtual ground arrays have divided the entire column width into smaller sections to eliminate extra ground paths created by programming more than one bit. Typically, the size of the smaller sections are sixteen columns wide with either eight bitlines and nine array source lines or nine bitlines and eight array source lines. However, it is often desirable to couple more than sixteen columns to an input/output device. Previous techniques to couple 64 columns to an input/output device have used four separate sixteen column sections with each section coupled to a first level 1 of 16 decoder and each 1 of 16 decoder coupled to a second level 1 of 4 decoder. The use of four separate sixteen column sections is area consuming since the sections must be spaced apart and require a total of 3 more source or drain diffusions than required in a single 64 column section. However, the area penalty using four sixteen column sections is less than the penalty incurred using a 1 of 64 decoder to decode a single 64 column section.